Computer Systems: A Programmer's Perspective (Global Edition): The ISA Contract and Architectural State

The Instruction Set Architecture (ISA) serves as a fundamental abstraction level and a formal contract between software and hardware. While high-level languages like C hide complexity, the ISA exposes the architectural state—the precise configuration of the processor's registers and memory.

1. The Architectural State

An x86-64 CPU defines its state through several key components:

Program Counter (%rip): Holds the address of the next instruction.
Integer Register File: 16 general-purpose registers (e.g., %rax, %rbx) storing 64-bit values.
Condition Codes: Flags (ZF, SF, CF, OF) for control flow.
Vector Registers: Such as YMM registers (256 bits) for SIMD operations.

2. Memory Abstraction

Machine code views memory as a massive byte-addressable array. While x86-64 supports 64-bit virtual addresses, current implementations often use a 48-bit address space ($2^{48}$ bytes). We categorize data sizes as Word (16-bit), Double word (32-bit), and Quad word (64-bit).

3. Evolution and Compatibility

Driven by Moore’s Law, Intel has evolved from the 8086 to Core i7 Haswell. The ISA ensures backward compatibility, allowing legacy machine code to execute on modern multi-core, hyperthreaded hardware.

TERMINAL bash — 80x24

> Ready. Click "Run" to execute.

QUESTION 1

Practice Problem 2.52: Convert Format A bits 0 011 000 (Sign:1, Exp:3, Frac:3) to the closest value in Format B (Sign:1, Exp:2, Frac:4). Use round-to-even.

0 01 0000

0 10 0000

0 11 1000

0 00 1111

✅ Correct!

In Format A (bias 3), 011 is exponent 0 ($2^0$), so value is 1.0. In Format B (bias 1), exponent 0 is represented by 01. 1.0 is 0 01 0000.

QUESTION 2

Which of the following assembly lines is valid for a 64-bit system?

movb %ebx, (%rax)

movq %rax, $0x123

movl %eax, (%rsp)

movw %cl, %ax

✅ Correct!

movl %eax, (%rsp) is valid; it moves a 32-bit double word into memory. Others fail due to size mismatches (ebx is 32-bit, movb is 8-bit) or trying to move into an immediate value.

QUESTION 3

If a processor requires 25 cycles for predictable branches and 45 cycles for random branches, what is the Branch Misprediction Penalty ($T_{MP}$)?

20 cycles

40 cycles

10 cycles

65 cycles

QUESTION 4

In the 'Guarded-Do' transformation of a while loop, what happens first?

The loop body executes once unconditionally.

An initial conditional branch checks if the loop should be skipped entirely.

The loop is converted into a switch statement.

The compiler uses a jump-to-middle strategy.

QUESTION 5

What is the primary function of the leaq instruction when not accessing memory?

To perform fast arithmetic like x + k*y.

To clear the condition code registers.

To move data between XMM registers.

To sign-extend a byte to a quad word.

✅ Correct!

leaq (Load Effective Address) uses address-computation hardware to perform additions and shifts without referencing memory.

Case Study: Complex Argument Handling

Analysis of Procedure Calls in ISO C99

You are reverse engineering a C program that uses complex numbers (ISO C99). A function complex_add receives two 128-bit structures (representing real and imaginary parts) and returns a result. In x86-64, you notice that %rdi is used for an address, even though the C prototype doesn't show an explicit pointer argument.

How are large complex structures typically passed as arguments to functions?

Solution:
While the first six small arguments (integers/pointers) fit in registers like %rdi and %rsi, large structures (like 128-bit complex types) are often passed by copying them onto the stack, or by the caller passing a pointer to the structure in a register.

How are complex values or large structs returned from a function in x86-64?

Solution:
For values larger than 64 bits that cannot fit in %rax, the caller allocates space on its own stack frame and passes the address of this space in %rdi. The callee then writes the return value directly to that memory location and returns the address in %rax.